(Solution) Clock Domain Crossing

Good morning all!

Hope you attempted our last question of the day on the very interesting topic of Clock Domain Crossing! Here are the answers I came up with, feel free to share yours below in the comments or provide any feedback:

1. In what stage of ASIC digital design (pre-synthesis, post-synthesis, post-PnR) would CDC checking typically occur? → Answer: typically done on RTL pre-synthesis. There are many reasons for this, but one key reason is not having to wait for synthesis to complete and also not having to modify the netlist if any issue is found, so industry tools such as Cadence Jasper Gold enable this to be done on RTL itself.

2. Name one tool used for CDC checking that you are familiar with? Can be any EDA vendor. Answer: Cadence Jasper Gold is one such example (there are more from other vendors).

3. Name one design construct used to prevent unforeseen issues that may arise due to CDC? Answer: A two-flop synchronizer can prevent the unwanted propagation of metastability to other parts of the circuit after clock domain crossing.

4. Is this classified as a functional verification or formal verification tool? Answer: Depending on the vendor, the tool could be a combination of both! Tools such as Jasper Gold use both functional and formal techniques to check for CDC issues. More info available here: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/system-design-verification/clock-domain-crossing-verification-wp.pdf

   Be on the lookout for our next question and feel free to comment below!