(Medium) Clock Domain Crossing - Semiconductors

Good evening, debuggers!

Hope you had a blast solving our last question of the day on constraints. A difficult one for sure!

One of the most difficult aspects of design verification interviews is the breadth of knowledge required to do well in them. Most software interviews today revolve around Leetcode-style coding questions and system design questions.

DV, on the other hand, is a different beast. Sure, there is overlap between software and digital DV. However, a DV interviewer may also ask trivia questions on literally any topic including UVM, CDC analysis, formal verification, possibly analog basics, System Verilog, metastability, synchronization, regression debug….the list goes on.

So, in addition to mastering Leetcode-style questions, we must also be knowledgeable about these various topics to succeed in DV interviews for top companies.

With that said, here is today’s question of the day: 

Explain the importance of CDC checking in the ASIC design flow and in particular, answer the following questions:

1. In what stage of ASIC digital design (pre-synthesis, post-synthesis, post-PnR) would CDC checking typically occur?

2. Name one tool used for CDC checking that you are familiar with? Can be any EDA vendor.

3. Name one design construct used to prevent unforeseen issues that may arise due to CDC?

4. Is this classified as a functional verification or formal verification tool?

Good luck!