(Solution) Classic System Verilog Question

Good evening!

Recall our last question of the day, a classic System Verilog question which is frequently asked in DV interviews and which you are very likely to see in your DV interview journey.

The answer to this need not be excessively complicated.

Reg is a Verilog variable type used to hold a value.

Wire is a Verilog net type used for continuous assignment by one or more drivers.

Logic is a System Verilog data type which can be used to both store a value (like reg) and continuous assignment (like wire), but should not be used for continuous assignment by multiple drivers. In that case, wire (or tri) should be used.

Note that there is no strict relationship between reg and sequential or combinational logic. For example, the following piece of code is combination but a must be declared as a reg since it needs to store the value until a or b change:

always @ (a or b) begin
    c = a & b;
end

Some more great info can be found at this link: