(Hard) Another Constraint Challenge

Good Afternoon Debuggers,

Hope you enjoyed solving our first Question of the Day which involved a clever use of const to create a System Verilog constraint.

Constraints are often one of the most frequently asked topics in verification interviews for top semiconductor companies as well as FAANG and startups.

So, here’s another one to flex your constraint-writing muscles:

Write a System Verilog constraint to generate a random 32-bit value with 10 contiguous bits as 0 and the remainder of the bits as 1.

Valid Output (10 contiguous 0s and remaining bits are 1): 11111111111111111111100000000001

Invalid Output (only 9 contiguous 0s)

11111111111111111111110000000001

Good luck!